Napier, Luke W. P. (2014) Develop process bus architecture for integrating sampled value IEDs. [USQ Project]
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Abstract
The recent interest within the power industry for the use of the IEC61850 standard has meant that the technology needed to implement this standard is at the forefront of most manufactures development projects. The most recent development are for devices used to implement the process bus component of the standard, described in part 9 of the standard. The implementation of this new technology into a Distribution Network Service Provider’s substation has additional challenges compared to that of a Transmission Network service Provider.
The implementation of a process bus architecture is a significant change from the existing practice. The critical nature of the system in which this change is occurring means that the impact of the technology will be heavily scrutinised by end users. Two key technical issues
were identified that would arise from the introduction of process bus technology into a substation.
The impact on the reliability of the system caused by replacing a simple connection practice between the instrument transformer and the protection relay with a communication network is one of the issues. Appropriately designing the process bus architecture by utilising
redundancy has provided a means so that the reliability of the process bus system exceeds that of the existing conventional system. The analyses of two-process bus architectures has been constructed as part of this project to demonstrate the reliability improvement.
The performance of the new devices introduced into the network needs to be understood so that any effect on the overall system is known. It has been identified that the merging unit that was tested as part of this project has shown a reduction in the performance of the analogue to
digital conversion of measured data based on transient response criteria.
To describe the performance of a merging unit such that the end user can predict the output of the device for different inputs, a mathematical model was developed. This model is a
second order transfer function approximation obtained from the transient response test results for a merging unit subjected to a DC step input. Minor gain errors were observed when testing the model with typical system signals such as the unsaturated sine waveform and a
saturated CT waveform.
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